VHDL
VHDL Online resources
VHDL Books There are dozens of great books talking about VHDL modeling, simulation and synthesis. Here are some of the…
VHDL
VHDL Coding Guidelines
Non-Synthesizable VHDL Code
RTL Synthesis is done by matching high level code against templates or patterns. It is important to use idioms that you…
VHDL
VLSI/ASIC/VHDL Interview Questions
1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the p…
VHDL
A Step-By-Step Methodical Approach for Efficient Mixed-Language IP Integration
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integra…
VITAL
VITAL and its Origins!
Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 19…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 7
Hints Avoid more package references than needed Keep all objects and subprograms in the nearest possible scope Keep loc…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 6
To Avoid common Warnings Store each VHDL unit into a separate file except package header and body Signal assignments fo…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 5
Critical Policies to Keep note! Balance clock to delta accuracy Pull-ups and pull-downs have to be modeled on chip leve…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 4
To Avoid common Errors A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 3
Portability Language for modeling should be VHDL-87 VHDL-93 keywords should not be used Verilog keywords should not be…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 2
When Compiling (VHDL): A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It…
VHDL
VHDL Interview Question(s)
What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produc…
VHDL
Comparison of VHDL to Other Hardware Description Languages
VHDL Disadvantages VHDL is verbose, complicated and confusing Many different ways of saying the same thing Constructs t…