Interview Questions
Interview Question - Bangalore
Assume a clock-gating scheme for turning off the clock in certain situations: 60% of the time, the main circuit has va…
Gated clocks
Timing
Clock Latency & clock skew
Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will obs…
Gated clocks
Adv and DisAdv of Gated Clocks
Advantges: used to save power by masking the clock to the flops. used in clock switching circuits. Reduces routing burd…
Synthesis
Low power design
Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate …