XVGA
Simple XVGA (1024x768) Controller in Verilog
module xvga(clk,hcount,vcount,hsync,vsync); input clk; // 64.8 Mhz output [10:0] hcount; output [9:0] vcount; …
Coding
Coding
“behavioural model” & “structural model”
The phrases "behavioural model" and "structural model" are commonly used for what we'll call &q…
Coding
Verilog code to detect if a 64bit pattern can be expressed using power of 2
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
Coding
Verilog Shift Register with Test Bench
module shifter (result, value_in, direction, type, length); output [7:0] result; input [7:0] value_in; input direction;…
Verilog
Verilog Awareness
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Verilog
Verilog Awareness
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Verilog
Verilog Blocking Vs Non Blocking, Myths and Facts
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…
Guidelines
Design Guidelines and Criteria for Digital Electronics
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amoun…