Verification challenge #1 (Solution)

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1. The circuit is correct. One of the assertions has a bug. All of the test-vectors pass without any assertion failures.
Solution: Yes, it is possible. None of the test vectors triggered the buggy assertion, the buggy assertion describes a situation that cannot occur (e.g., “if the TV is on and the power is not connected.”), or a bug in the instrumentation code masked the bug in the assertion.
2. The circuit is correct. All of the assertions are correct. Some of the test-vectors fail one of the assertions.
Solution: Yes, it is possible. A bug in the instrumentation code could cause an assertion to fail when it should not, or an “illegal” test-vector is run (illegal in that it violates the constraints or assumptions about the input data, for example sending valid data while reset is asserted).